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?002 fairchild semiconductor corporation 1 www.fairchildsemi.com october 2002 ace1502 product family arithmetic controller engine (acex) for low power applications ace1502 product family rev. 1.7 ace1502 product family arithmetic controller engine (acex) for low power applications general description the ace1502 (arithmetic controller engine) family of microcon- trollers is a dedicated programmable monolithic integrated circuit for applications requiring high performance, low power, and small size. it is a fully static part fabricated using cmos technology. the ace1502 product family has an 8-bit microcontroller core, 64 bytes of ram, 64 bytes of data eeprom and 2k bytes of code eeprom. its on-chip peripherals include a multifunction 16-bit timer, a watchdog/idle timer, and programmable under- voltage detection circuitry. on-chip clock and reset functions reduce the number of required external components. the ace1502 product family is available in 8- and 14-pin soic, tssop and dip packages. features arithmetic controller engine 2k bytes on-board code eeprom 64 bytes data eeprom 64 bytes ram watchdog multi-input wake-up on all eight general purpose i/o pins 16-bit multifunction timer with difference capture hardware bit?oder (hbc) on-chip oscillator ?no external components ?1? instruction cycle time +/-2% accuracy instruction set geared for block encryption on-chip power-on reset programmable read and write disable functions memory mapped i/o 32-level low voltage detection brown-out reset software selectable i/o option ?push-pull outputs with tri-state option ?weak pull-up or high impedance inputs fully static cmos ?low power halt mode (100na @ 2.7v) ?power saving idle mode single supply operation ?1.8-3.6v 40 years data retention 1.8v data eeprom min writing voltage 1,000,000 data changes 8- and 14-pin soic, tssop and dip packages in-circuit programming block and connection diagram 1. 100nf decoupling capacitor recommended 2. available only in the 14-pin package option vcc 1 power-on reset brown-out reset/low battery detect programming interface 2k bytes of code eeprom 64 bytes of data eeprom 64 bytes of ram 12-bit timer0 with watchdog timer 16-bit multi-function timer1 with difference capture halt & idle power saving modes gport general purpose i/o with multi- input wakeup internal oscillator gnd 1 reset 2 (cko) g0 (cki) g1 g4 g6 2 g7 2 g3 hardware bit-coder (t1/tx) g2 (tx) g5 ace1502 core (4 interrupt sources and vectors)
2 www.fairchildsemi.com ace1502 product family rev. 1.7 ace1502 product family arithmetic controller engine (acex) for low power applications figure 2. acex application example (remote keyless entry) figure 3. ace1502 8-pin soic and dip device pinout a) normal mode operation b) programming mode operation figure 4. ace1502 8-pin tssop device pinout a) normal mode operation b) programming mode operation figure 5. ace1502 14-pin soic, tssop and dip device pinout a) normal mode operation b) programming mode operation v cc v cc optional led rf stage rf interface g0 g1 g5 g2 gnd g4 g3 load vcc gnd sft_out cki 1 2 3 45 6 7 8 sft_in nc/vcc nc g3 vcc gnd g2 g1 1 2 3 45 6 7 8 g4 g0 g5 1 2 3 45 6 7 8 g5 g0 g1 g2 g4 g3 vcc gnd gnd sft_out cki nc nc/vcc 1 2 3 45 6 7 8 vcc load sft_in g3 vcc gnd g1 1 2 3 4 5 6 78 g4 nc 9 10 11 12 13 14 g6 g7 g5 nc nc g2 reset g0 load vcc gnd cki 1 2 3 4 5 6 78 sft_in nc nc 9 10 11 12 13 14 nc nc nc/vcc nc nc sft_out reset
ace1502 product family arithmetic controller engine (acex) for low power applications 3 www.fairchildsemi.com ace1502 product family rev. 1.7 2. electrical characteristics absolute maximum ratings ambient storage temperature -65 c to +150 c input voltage -0.3v to v cc + 0.3v lead temperature (10s max) +300 c electrostatic discharge on all pins 2000v min operating conditions relative humidity (non-condensing) 95% eeprom write limits see dc electrical characteristics ace1502 dc electrical characteristics, v cc = 1.8 to 3.6v all measurements are valid for ambient operating temperature unless otherwise stated. 3. icc active current is dependant on the program code. 4. based on a continuous idle looping program. part number operating voltage ambient operating temperature ace1502e 1.8 to 3.6v -40 c to +85 c ace1502v 1.8 to 3.6v -40 c to +125 c symbol parameter conditions min typ max units icc 3 suppy current - no data eeprom write in progress 1.8v 2.2v 2.7v 3.6v 0.4 0.4 0.5 0.6 0.6 0.6 0.7 1.0 ma ma ma ma icc h halt mode current 2.7v @ 25 c 2.7v @ -40 c to +85 c 100 400 5000 na na 3.6v @ 25 c 3.6v @ -40 c to +85 c 0.25 1000 10 na a icc l 4 idle mode current 1.8v 3.6v 210 250 400 a a vcc w eeprom write voltage code eeprom in programming mode 3.0 3.3 3.6 v data eeprom in operating mode 1.8 3.6 v s vcc power supply slope 1s/v 10ms/v v il input low with schmitt trigger buffer vcc = 2.2 - 3.6v 0.2vcc v vcc < 2.2v 0.15vcc v v ih input high with schmitt trigger buffer vcc = 1.8 - 3.6v 0.8vcc v i ip input pull-up current vcc = 3.6v, v in = 0v 30 65 350 a i tl tri-state leakage vcc = 3.6v 2 200 na v ol output low voltage: g0, g1, g2, g3, g4, g5, g6, g7 vcc = 1.8 - 2.7v 2 ma sink 0.2vcc v output low voltage: g0, g1, g2, g3, g4, g5, g6, g7 vcc = 3.3 - 3.6v 7.0 ma sink 0.2vcc v v oh output high voltage: g0, g1, g2, g3, g4, g5, g6, g7 vcc = 2.2 - 2.7v 2 ma source 0.8vcc v output high voltage: g0, g1, g2, g3, g4, g5, g6, g7 vcc = 3.3 - 3.6v 7 ma source 0.8vcc v
4 www.fairchildsemi.com ace1502 product family rev. 1.7 ace1502 product family arithmetic controller engine (acex) for low power applications ace1502 ac electrical characteristics, vcc = 1.8 to 3.6v all measurements are valid for ambient operating temperature unless otherwise stated. 5. the maximum permissible frequency is guaranteed by design but is not 100% tested 6. the parameter is characterized but is not 100% tested, contact fairchild for additional characterization data. ace1502 electrical characteristics for programming all data valid at ambient temperature between 3.0v and 3.6v. the following characteristics are guaranteed by design but are not 100% tested. see eeprom write time in the ac electrical characteristics for de nition of the programming ready time. ace1502 low battery detect (lbd) characteristics, vcc = 1.8 to 3.6v ace1502 brown-out reset (bor) characteristics, vcc = 1.8 to 3.6v parameter conditions min typ max units instruction cycle time from internal clock - setpoint 3.3v at +25 c 0.98 1.0 1.02 s internal clock frequency variation 1.8v to 3.6v at constant temperature 1.2 % 1.8v to 3.6v at full temperature range (note 6) 6 % crystal oscillator frequency (note 5) 25 mhz external clock frequency (note 5) 8 mhz eeprom write time 5.5 10 ms internal clock start up time (note 6) 2 ms oscillator start up time (note 6) 2400 cycles parameter description min max units t hi clock high time 500 dc ns t lo clock low time 500 dc ns t dis shift_in setup time 100 ns t dih shift_in hold time 100 ns t dos shift_out setup time 100 ns t doh shift_out hold time 900 ns t reset power on reset time 3.2 4.5 ms t load1 , t load2 , t load3 , t load4 load timing 5 s parameter conditions min typ max units lbd voltage threshold variation -40 c to +85 c -5 +5 % parameter conditions min typ max units bor voltage threshold variation -40 c to +85 c 1.72 1.83 1.92 v
5 www.fairchildsemi.com ace1502 product family rev. 1.7 ace1502 product family arithmetic controller engine (acex) for low power applications ac & dc electrical characteristic graphs the graphs in this section are for design guidance and are based on preliminary test data. figure 6. internal oscillator frequency figure 7. lbd and bor threshold levels internal oscillator frequency vs. temperature -40 0 25 85 125 temperature [ c] frequency (mhz) 1.93 1.94 1.95 1.96 1.97 1.98 1.99 2 2.01 3.6v 3.3v 2.8v 2.6v 2.2v 2.0v 1.8v lbd levels 1,16 and 32 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 0 25 85 125 -40 0 25 85 125 temperature [ c] voltage (v) level 1 level 16 level 32 bor level 1.800 1.805 1.810 1.815 1.820 1.825 1.830 1.835 1.840 temperature [ c] voltage (v) bor level
6 www.fairchildsemi.com ace1502 product family rev. 1.7 ace1502 product family arithmetic controller engine (acex ) for low power applications figure 8. icc active figure 9. halt mode currents icc active (no data eeprom writes) vs. temperature 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 -40 0 25 85 125 -40 0 25 85 125 temperature [ c] current (ma) 4.0v 3.6v 2.7v 2.2v 1.8v 1.6v icc active (data eeprom writes) vs. temperature 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 temperature [ c] current (ma) 4.0v 3.6v 2.7v 2.2v 1.8v 1.6v halt current vs. temperature 0.000 2.000 4.000 6.000 8.000 10.000 12.000 14.000 16.000 18.000 20.000 -40 0 25 85 125 temperature [ c] icc halt (a) 4.0v 3.6v 2.7v 2.2v 1.8v 1.6v
7 www.fairchildsemi.com ace1502 product family rev. 1.7 ace1502 product family arithmetic controller engine (acex ) for low power applications figure 10. idle mode currents figure 11. v ol /v oh vs. current idle mode current 0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00 -40 0 25 85 125 temperature [ c] icc idle [ a] 4.0v 3.6v 2.7v 2.2v 1.8v 1.6v 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 4.0v 3.6v 2.7v 2.2v 1.8v 02 57 91215 i oh current (ma) v oh vs. i oh @ 25 c v oh (v) 0.00 0.50 1.00 1.50 2.00 2.50 3.00 02 57 91215 i ol (ma) v ol vs. i ol v ol (v) 3.6v 4.0v 2.7v 2.2v 1.8v
ace1502 product family arithmetic controller engine (acex ) for low power applications 8 www.fairchildsemi.com ace1502 product family rev. 1.7 3. arithmetic controller core the acex microcontroller core is speci cally designed for low cost applications involving bit manipulation, shifting and block encryption. it is based on a modi ed harvard architecture meaning peripheral, i/o, and ram locations are addressed sep- arately from instruction data. the core differs from the traditional harvard architecture by aligning the data and instruction memory sequentially. this allows the x-pointer (12-bits) to point to any memory location in either segment of the memory map. this modi cation improves the overall code ef ciency of the acex microcontroller and takes advantage of the exibility found on von neumann style machines. 3.1 cpu registers the acex microcontroller has ve general-purpose registers. these registers are the accumulator (a), x-pointer (x), pro- gram counter (pc), stack pointer (sp), and status register (sr). the x, sp, and sr registers are all memory-mapped. figure 12. programming model 3.1.1 accumulator (a) the accumulator is a general-purpose 8-bit register that is used to hold data and results of arithmetic calculations or data manip- ulations. 3.1.2 x-pointer (x) the x-pointer register allows for a 12-bit indexing value to be added to an 8-bit offset creating an effective address used for reading and writing between the entire memory space. (soft- ware can only read from code eeprom.) this provides soft- ware with the exibility of storing lookup tables in the code eeprom memory space for the core s accessibility during nor- mal operation. the acex core allows software to access the entire 12-bit x- pointer register using the special x-pointer instructions e.g. ld x, #000h. (see table 8.) however, software may also access the register through any of the memory-mapped instructions using the xhi (x[11:8]) and xlo (x[7:0]) variables located at 0xbe and 0xbf, respectively. (see table 10.) the x register is divided into two sections. the 11 least signi - cant bits (lsbs) of the register is the address of the program or data memory space. the most signi cant bit (msb) of the reg- ister is write only and selects between the data (0x000 to 0x0ff) or program (0x800 to 0xfff) memory space. example: if bit 11 = 0, then the ld a, [00,x] instruction will take a value from address range 0x000 to 0x0ff and load it into a. if bit 11 = 1, then the ld a, [00,x] instruction will take a value from address range 0x800 to 0xfff and load it into a. the x register can also serve as a counter or temporary storage register. however, this is true only for the 11-lsbs since the 12 th bit is dedicated for memory space selection. 3.1.3 program counter (pc) the 11-bit program counter register contains the address of the next instruction to be executed. after a reset, if in normal mode the program counter is initialized to 0x800. 3.1.4 stack pointer (sp) the acex microcontroller has an automatic program stack with a 4-bit stack pointer. the stack can be initialized to any location between addresses 0x30-0x3f. normally, the stack pointer is initialized by one of the rst instructions in an application pro- gram. after a reset, the stack pointer is defaulted to 0xf pointing to address 0x3f. the stack is con gured as a data structure which decrements from high to low memory. each time a new address is pushed onto the stack, the core decrements the stack pointer by two. each time an address is pulled from the stack, the core incre- ments the stack pointer is by two. at any given time, the stack pointer points to the next free location in the stack. when a subroutine is called by a jump to subroutine (jsr) instruction, the address of the instruction is automatically pushed onto the stack least signi cant byte rst. when the 0 7 0 0 0 3 10 11 00 n h c z g r a x pc sp sr 8-bit accumulator register 4-bit stack pointer 8-bit status register negative flag half carry flag (from bit 3) carry flag (from msb) zero flag (bit 4 ) ready flag (from eeprom) global interrupt enable 11-bit program counter 12-bit x pointer register
ace1502 product family arithmetic controller engine (acex ) for low power applications 9 www.fairchildsemi.com ace1502 product family rev. 1.7 subroutine is nished, a return from subroutine (ret) instruction is executed. the ret instruction pulls the previously stacked return address from the stack and loads it into the program counter. execution then continues at the recovered return address. 3.1.5 status register (sr) the 8-bit status register (sr) contains four condition code indi- cators (c, h, z, and n), one interrupt masking bit (g), and an eeprom write ag (r.) the condition codes are automatically updated by most instructions. (see table 9.) carry/borrow (c) the carry ag is set if the arithmetic logic unit (alu) performs a carry or borrow during an arithmetic operation and by its dedi- cated instructions. the rotate instruction operates with and through the carry bit to facilitate multiple-word shift operations. the ldc and invc instructions facilitate direct bit manipulation using the carry ag. half carry (h) the half carry ag indicates whether an over ow has taken place on the boundary between the two nibbles in the accumu- lator. it is primarily used for binary coded decimal (bcd) arith- metic calculation. zero (z) the zero ag is set if the result of an arithmetic, logic, or data manipulation operation is zero. otherwise, it is cleared. negative (n) the negative ag is set if the msb of the result from an arith- metic, logic, or data manipulation operation is set to one. other- wise, the ag is cleared. a result is said to be negative if its msb is a one. interrupt mask (g) the interrupt request mask (g) is a global mask that disables all maskable interrupt sources. if the g bit is cleared, interrupts can become pending, but the operation of the core continues uninterrupted. however, if the g bit is set an interrupt is recog- nized. after any reset, the g bit is cleared by default and can only be set by a software instruction. when an interrupt is rec- ognized, the g bit is cleared after the pc is stacked and the interrupt vector is fetched. once the interrupt is serviced, a return from interrupt instruction is normally executed to restore the pc to the value that was present before the interrupt occurred. the g bit is the reset to one after a return from inter- rupt is executed. although the g bit can be set within an inter- rupt service routine, nesting interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. 3.2 interrupt handling when an interrupt is recognized, the current instruction com- pletes its execution. the return address (the current value in the program counter) is pushed onto the stack and execution con- tinues at the address speci ed by the unique interrupt vector (see table 10.). this process takes ve instruction cycles. at the end of the interrupt service routine, a return from interrupt (reti) instruction is executed. the reti instruction causes the saved address to be pulled off the stack in reverse order. the g bit is set and instruction execution resumes at the return address. the acex microcontroller is capable of supporting four inter- rupts. three are maskable through the g bit of the sr and the fourth (software interrupt) is not inhibited by the g bit (figure 13.) the software interrupt is generated by the execution of the intr instruction. once the intr instruction is executed, the acex core will interrupt whether the g bit is set or not. the intr interrupt is executed in the same manner as the other maskable interrupts where the program counter register is stacked and the g bit is cleared. this means, if the g bit was enabled prior to the software interrupt the reti instruction must be used to return from interrupt in order to restore the g bit to its previous state. however, if the g bit was not enabled prior to the software interrupt the ret instruction must be used. in case of multiple interrupts occurring at the same time, the acex microcontroller core has prioritized the interrupts. the interrupt priority sequence in shown in table 7. table 7: interrupt priority sequence figure 13. basic interrupt structure priority (4 highest, 1 lowest) interrupt 4 miw (edgei) 3 timer0 (tmri0) 2 timer1 (tmri1) 1 software (intr) t1pnd t0pnd wkpnd t1en t0int en wkint en g intr t1 t0 miw interrupt pending flags interrupt enable bits global interrupt enable interrupt interr upt source with prior ity
ace1502 product family arithmetic controller engine (acex ) for low power applications 10 www.fairchildsemi.com ace1502 product family rev. 1.7 3.3 addressing modes the acex microcontroller has seven addressing modes indexed, indirect, direct, immediate, absolute jump, and relative jump. indexed the instruction allows an 8-bit unsigned offset value to be added to the 11-lsbs of the x-pointer yielding a new effective address. this mode can be used to address either data or pro- gram memory space. indirect the instruction allows the x-pointer to address any location within the data memory space. direct the instruction contains an 8-bit address eld that directly points to the data memory space as an operand. immediate the instruction contains an 8-bit immediate eld as an operand. inherent this instruction has no operands associated with it. absolute the instruction contains an 11-bit address that directly points to a location in the program memory space. there are two oper- ands associated with this addressing mode. each operand con- tains a byte of an address. this mode is used only for the long jump (jmp) and jsr instructions. relative this mode is used for the short jump (jp) instructions where the operand is a value relative to the current pc address. with this instruction, software is limited to the number of bytes it can jump, -31 or +32. table 8. instruction addressing modes instruction immediate direct indexed indirect inherent relative absolute adc add and or subc xor a, # a, # a, # a, # a, # a, # a, m a, m a, m a, m a, m a, m a, [#, x] a, [#, x] a, [#, x] a, [#, x] a, [#, x] a, [#, x] a, [x] a, [x] a, [x] a, [x] a, [x] a, [x] clr inc dec m m m a a a x x x ifeq ifgt ifne iflt a, # a, # a, # x, # x, # x, # x, # m,# m,# a, m a, m a, m a, [#, x] a, [#, x] a, [#, x] a, [x] a, [x] a, [x] sc rc ifc ifnc invc ldc stc #, m #, m no-op no-op no-op no-op no-op rlc rrc m m a a ld st a, # m, # x, # a, m a, m m, m a, [#, x] a, [#, x] a, [x] a, [x] nop no-op ifbit #, a #, m [#, x] ifnbit sbit rbit #, a #, m #, m #, m [#, x] [#, x] [#, x] jp jsr jmp ret reti intr [#, x] [#, x] no-op no-op no-op rel m m
ace1502 product family arithmetic controller engine (acex ) for low power applications 11 www.fairchildsemi.com ace1502 product family rev. 1.7 table 9. instruction cycles and bytes mnemonic operand bytes cycles flags affected adc a, [x] 1 1 c,h,z,n adc a, [#,x] 2 3 c,h,z,n adc a, m 2 2 c,h,z,n adc a, # 2 2 c,h,z,n add a, [x] 1 1 z,n add a, [#,x] 2 3 z,n add a, m 2 2 z,n add a, # 2 2 z,n and a, [x] 1 1 z,n and a, [#,x] 2 3 z,n and a, m 2 2 z,n and a, # 2 2 z,n clr x 1 1 z clr a 1 1 c,h,z,n clr m 2 1 c,h,z,n dec x 1 1 z dec a 1 1 z,n dec m 2 2 z,n ifbit #, a 1 1 none ifbit #, m 2 2 none ifbit #, [x] 1 1 none ifc 1 1 none ifeq a, [#, x] 2 3 none ifeq a, [x] 1 1 none ifeq a, # 2 2 none ifeq a, m 2 2 none ifeq m, # 3 3 none ifeq x, # 3 3 none ifgt a, [#, x] 2 3 none ifgt a, [x] 1 1 none ifgt a, # 2 2 none ifgt a, m 2 2 none ifgt x, # 3 3 none iflt x, # 3 3 none ifnbit #, a 1 1 none ifnbit #, m 2 2 none ifnbit #, [x] 1 1 none ifnc 1 1 none ifne a, [#, x] 2 3 none ifne a, [x] 1 1 none ifne a, # 2 2 none ifne a, m 2 2 none ifne x, # 3 3 none ifne m, # 3 3 none inc a 1 1 z,n inc m 2 2 z,n mnemonic operand bytes cycles flags affected inc x 1 1 z intr 1 5 none invc 1 1 c jmp m 3 4 none jmp [#, x] 2 3 none jp 1 1 none jsr m 3 5 none jsr [#, x] 2 5 none ld a, # 2 2 none ld a, [#,x] 2 3 none ld a, [x] 1 1 none ld a, m 2 2 none ld m, # 3 3 none ld m, m 3 3 none ld x, # 3 3 none ldc #, m 2 2 c nop 1 1 none or a, [x] 1 1 z, n or a, [#,x] 2 3 z,n or a, m 2 2 z,n or a, # 2 2 z,n rbit #, [x] 1 2 z,n rbit #, m 2 2 z,n rc 1 1 c,h ret 1 5 none reti 1 5 none rlc a 1 1 c,z,n rlc m 2 2 c,z,n rrc a 1 1 c,z,n rrc m 2 2 c,z,n sbit #, [x] 1 2 z,n sbit #, m 2 2 z,n sc 1 1 c,h st a, [#,x] 2 3 none st a, [x] 1 1 none st a, m 2 2 none stc #, m 2 2 z,n subc a, [x] 1 1 c,h,z,n subc a, [#,x] 2 3 c,h,z,n subc a, m 2 2 c,h,z,n subc a, # 2 2 c,h,z,n xor a, [x] 1 1 z,n xor a, [#,x] 2 3 z,n xor a, m 2 2 z,n xor a, # 2 2 z,n
12 www.fairchildsemi.com ace1502 product family rev. 1.7 ace1502 product family arithmetic controller engine (acex ) for low power applications 3.4 memory map all i/o ports, peripheral registers, and core registers (except the accumulator and the program counter) are mapped into the me mory space. table 10. memory mapped registers address memory space block contents 0x00 - 0x3f data sram data ram 0x40 - 0x7f data eeprom data eeprom 0x80-0x9f data reserved 0xa0 data hbc hbcntrl register 0xa1 data hbc pscale register 0xa2 data hbc hpattern register 0xa3 data hbc lpattern register 0xa4 data hbc bpsel register 0xa7 data timer1 t1rblo register 0xa8 data timer1 t1rbhi register 0xa9 data hbc dat0 register 0xaa data timer1 t1ralo register 0xab data timer1 t1rahi register 0xac data timer1 tmr1lo register 0xad data timer1 tmr1hi register 0xae data timer1 t1cntrl register 0xaf data miw wkedg register 0xb0 data miw wkpnd register 0xb1 data miw wken register 0xb2 data i/o portgd register 0xb3 data i/o portgc register 0xb4 data i/o portgp register 0xb5 data timer0 wdsvr register 0xb6 data timer0 t0cntrl register 0xb7 data clock halt mode register 0xb8-0xba data reserved 0xbb data init. register initialization register 1 0xbc data init. register initialization register 2 0xbd data lbd lbd register 0xbe data core xhi register 0xbf data core xlo register 0xc0 data clock power mode clear (pmc) register 0xce data core sp register 0xcf data core status register (sr) 0xd0 - 0xff data reserved 0x800 - 0xff5 program eeprom code eeprom 0xff6 - 0xff7 program core timer0 interrupt vector 0xff8 - 0xff9 program core timer1 interrupt vector 0xffa - 0xffb program core miw interrupt vector 0xffc - 0xffd program core soft interrupt vector 0xffe - 0xfff program reserved
ace1502 product family arithmetic controller engine (acex ) for low power applications 13 www.fairchildsemi.com ace1502 product family rev. 1.7 3.5 memory the acex microcontroller has 64 bytes of sram and 64 bytes of eeprom available for data storage. the device also has 2k bytes of eeprom for program storage. software can read and write to sram and data eeprom but can only read from the code eeprom. while in normal mode, the code eeprom is protected from any writes. the code eeprom can only be rewritten when the device is in program mode and if the write disable (wdis) bit of the initialization register is not set to 1. while in normal mode, the user can write to the data eeprom array by 1) polling the ready (r) ag of the sr, then 2) execut- ing the appropriate instruction. if the r ag is 1, the data eeprom block is ready to perform the next write. if the r ag is 0, the data eeprom is busy. the data eeprom array will reset the r ag after the completion of a write cycle. attempts to read, write, or enter halt/idle mode while the data eeprom is busy (r = 0) can affect the current data being written. 3.6 initialization registers the acex microcontroller has two 8-bit wide initialization registers. these registers are read from the memory space on power-up to initialize certain on-chip peripherals. figure 14 provides a detailed description of initialization register 1. the initialization register 2 is used to trim the internal oscillator to its appropriate frequency. this register is pre-programmed in the factory to yield an internal instruction clock of 1mhz. the initialization registers 1 and 2 can be read from and written to during programming mode. however, re-trimming the inter- nal oscillator (writing to the initialization register 2) once it has left the factory is discouraged . figure 14. initialization register 1 (0) rdis if set, disables attempts to read the contents from the memory while in programming mode. once this bit is set, it is no longer possible to unset this option even though the write disable option is not enabled. (1) wdis if set, disables attempts to write new contents to the memory while in programming mode (2) ubd if set, the device will not allow any writes to occur in the upper block of data eeprom (0x60-0x7f) (3) lbden if set, the low battery detection circuit is enabled (4) boren if set, allows a bor to occur if vcc falls below the voltage reference level (5) wden if set, enables the on-chip processor watchdog circuit (6) cmode[1] clock mode select bit 1 (see table 16) (7) cmode[0] clock mode select bit 0 (see table 16) 4. timer 1 timer 1 is a versatile 16-bit timer that can operate in one of four modes: pulse width modulation (pwm) mode, which generates pulses of a speci ed width and duty cycle external event counter mode, which counts occurrences of an external event standard input capture mode, which measures the elapsed time between occurrences of external events difference input capture mode, which automatically mea- sures the difference between edges. timer 1 contains a 16-bit timer/counter register (tmr1), a 16-bit auto-reload/capture register (t1ra), a secondary 16-bit auto- reload register (t1rb), and an 8-bit control register (t1cntrl). all register are memory-mapped for simple access through the core with both the 16-bit registers organized as a pair of 8-bit register bytes {tmr1hi, tmr1lo}, {t1rahi, t1ralo}, and {t1rbhi, t1rblo}. depending on the operating mode, the timer contains an external input or output (t1) that is multiplexed with the i/o pin g2. by default, the tmr1 is reset to 0xffff, t1ra/t1rb is reset to 0x0000, and t1cntrl is reset to 0x00. the timer can be started or stopped through the t1cntrl reg- ister bit t1c0. when running, the timer counts down (decre- ments) every clock cycle. depending on the operating mode, the timer s clock is either the instruction clock or a transition on the t1 input. in addition, occurrences of timer under ow (transi- tions from 0x0000 to 0xffff/t1ra/t1rb value) can either generate an interrupt and/or toggle the t1 output pin. timer 1 s interrupt (tmri1) can be enabled by interrupt enable (t1en) bit in the t1cntrl register. when the timer interrupt is enabled, depending on the operating mode, the source of the interrupt is a timer under ow and/or a timer capture. 4.1 timer control bits reading and writing to the t1cntrl register controls the timer s operation. by writing to the control bits, the user can enable or disable the timer interrupts, set the mode of operation, and start or stop the timer. the t1cntrl register bits are described in table 11 and table 12. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmode[0] cmode[1] wden boren ldben ubd wdis rdis
ace1502 product family arithmetic controller engine (acex ) for low power applications 14 www.fairchildsemi.com ace1502 product family rev. 1.7 table 11. timer 1 control register (t1cntrl) table 12. timer 1 operating modes 4.2 mode 1: pulse width modulation (pwm) mode in the pwm mode, the timer counts down at the instruction clock rate. when an under ow occurs, the timer register is reloaded from t1ra/t1rb and the count down proceeds from the loaded value. at every under ow, a pending ag (t1pnd) located in the t1cntrl register is set. software must then clear the t1pnd ag and load the t1ra/t1rb register with an alternate pwm value (if desired.) in addition, the timer can be con gured to toggle the t1 output bit upon under ow. con gur- ing the timer to toggle t1 results in the generation of a signal outputted from port g2 with the width and duty cycle controlled by the values stored in the t1ra/t1rb. a block diagram of the timer s pwm mode of operation is shown in figure 15. the pwm timer can be con gured to use the t1ra register only for auto-reloading the timer registers or can be con gured to use both t1ra and t1rb alternately. if the t1rben bit of the t1cntrl register is 0, the pwm timer will reload using only t1ra ignoring any value store in the t1rb register. however, if the t1rben bit is 1 the pwm timer will be reloaded using both the t1ra and t1rb registers. a hardware select logic is imple- mented to select between t1ra and t1rb alternately, always starting with t1ra, every timer under ows to auto-reload the timer registers. this feature is useful when a signal with variable duty cycle needs to be generated without software intervention. the timer has one interrupt (tmri1) that is maskable through the t1en bit of the t1cntrl register. however, the core is only interrupted if the t1en bit and the g (global interrupt enable) bit of the sr is set. if interrupts are enabled, the timer will gen- erate an interrupt each time t1pnd ags is set (whenever the timer under ows provided that the pending ag was cleared.) the interrupt service routine is responsible for proper handling of the t1pnd ag and the t1en bit. the interrupt will be synchronous with every rising and falling edge of the t1 output signal. generating interrupts only on ris- ing or falling edges of t1 is achievable through appropriate han- dling of the t1en bit or t1pnd ag through software. t1cntrl register bit name function bit 7 t1c3 timer timer1 control bit 3 (see table 12) bit 6 t1c2 timer timer1 control bit 2 (see table 12) bit 5 t1c1 timer timer1 control bit 1 (see table 12) bit 4 t1c0 timer timer1 run: 1= start timer, 0 = stop timer; or timer timer1 under ow interrrupt pending ag in input capture mode bit 3 t1pnd timer1 interrupt pending ag: 1 = timer1 interrupt pending, 0 = timer1 interrupt not pending bit 2 t1en timer1 interrupt enable bit: 1 = timer1 interrupt enabled, 0 = timer1 interrupt disabled bit 1 m1s1 capture type: 0 = pulse capture, 1 = cycle capture (see table 12) bit 0 t1rben pwm mode: 0 = timer1 reload on t1ra, 1 = timer1 reload on t1ra and t1rb (always starting with t1ra) t1 c3 t1 c2 t1 c1 m4 s1 t1 rb timer mode source interrupt timer counts-on 0 0 0 x x mode 2 timer1 under ow t1 pos. edge 0 0 1 x x mode 2 timer1 under ow t1 neg. edge 1 0 1 x 0 mode 1 t1 toggle autoreload t1ra instruction clock 1 0 0 x 0 mode 1 no t1 toggle autoreload t1ra instruction clock 1 0 1 x 1 mode 1 t1 toggle autoreload t1ra/t1rb instruction clock 1 0 0 x 1 mode 1 no t1 toggle autoreload t1ra/t1rb instruction clock 0 1 0 x x mode 3 captures: t1 pos edge pos. t1 edge instruction clock 0 1 1 x x mode 3 captures: t1 neg edge neg. t1 edge instruction clock 1100x mode 4 pos. to neg. instruction clock 1101x mode 4 pos. to pos. instruction clock 1110x mode 4 neg. to pos. instruction clock 1111x mode 4 neg. to neg. instruction clock
ace1502 product family arithmetic controller engine (acex ) for low power applications 15 www.fairchildsemi.com ace1502 product family rev. 1.7 the following steps show how to properly con gure timer 1 to operate in the pwm mode. for this example, the t1 output sig- nal is toggled with every timer under ow and the high and low times for the t1 output can be set to different values. the t1 output signal can start out either high or low depending on the con guration of g2; the instructions below are for starting with the t1 output high. follow the instructions in parentheses to start the t1 output low. 1. con gure t1 as an output by setting bit 2 of portgc. - sbit 2, portgc ; con gure g2 as an output 2. initialize t1 to 1 (or 0) by setting (or clearing) bit 2 of portgd. - sbit 2, portgd ; set g2 high 3. load the initial pwm high (low) time into the timer register. - ld tmr1lo, #6fh ; high (low) for 1.391ms (1mhz clock) - ld tmr1hi, #05h 4. load the pwm low (high) time into the t1ra register. - ld t1ralo, #2fh ; low (high) for .303ms (1mhz clock) - ld t1rahi, #01h 5. write the appropriate control value to the t1cntrl register to select pwm mode with t1 toggle, to clear the enable bit and pending ag, and to start the timer. (see table 11 and table 12.) - ld t1cntrl, #0b0h ; setting the t1c0 bit starts the timer 6. after every under ow, load t1ra with alternate values. if the user wishes to generate an interrupt on a t1 output transi- tion, reset the pending ags and then enable the interrupt using t1en. the g bit must also be set. the interrupt service routine must reset the pending ag and perform whatever processing is desired. - rbit t1pnd, t1cntrl ; t1pnd equals 3 - ld t1ralo, #6fh ; high (low) for 1.391ms (1mhz clock) - ld t1rahi, #05h figure 15. pulse width modulation mode 4.3 mode 2: external event counter mode the external event counter mode operates similarly to the pwm mode; however, the timer is not clocked by the instruction clock but by transitions of the t1 input signal. the edge is selectable through the t1c1 bit of the t1cntrl register. a block diagram of the timer s external event counter mode of operation is shown in figure 16. the t1 input should be connected to an external device that generates a positive/negative-going pulse for each event. by clocking the timer through t1, the number of positive/negative transitions can be counted therefore allowing software to cap- ture the number of events that occur. the input signal on t1 must have a pulse width equal to or greater than one instruction clock cycle. the counter can be con gured to sense either positive-going or negative-going transitions on the t1 pin. the maximum fre- quency at which transitions can be sensed is one-half the fre- quency of the instruction clock. as with the pwm mode, when the counter under ows the counter is reloaded from the t1ra register and the count down proceeds from the loaded value. at every under ow, a pending ag (t1pnd) located in the t1cntrl register is set. software must then clear the t1pnd ag and can then load the t1ra register with an alternate value. the counter has one interrupt (tmri1) that is maskable through the t1en bit of the t1cntrl register. however, the core is only interrupted if the t1en bit and the g (global interrupt enable) bit of the sr is set. if interrupts are enabled, the counter will generate an interrupt each time the t1pnd ag is set (when- ever timer under ows provided that the pending ag was cleared.) the interrupt service routine is responsible for proper handling of the t1pnd ag and the t1en bit. the following steps show how to properly con gure timer 1 to operate in the external event counter mode. for this example, the counter is clocked every falling edge of the t1 input signal. follow the instructions in parentheses to clock the counter every rising edge. 1. con gure t1 as an input by clearing bit 2 of portgc. - rbit 2, portgc ; con gure g2 as an input 2. initialize t1 to input with pull-up by setting bit 2 of portgd. - sbit 2, portgd ; set g2 high 3. enable the global interrupt enable bit. - sbit 4, status 4. load the initial count into the tmr1 and t1ra registers. when the number of external events is detected, the counter will reach zero; however, it will not under ow until the next event is detected. to count n pulses, load the value n-1 into the registers. if it is only necessary to count the number of occurrences and no action needs to be taken at a particular count, load the value 0xffff into the registers. - ld tmr1lo, #0ffh - ld tmr1hi, #0ffh - ld t1ralo, #0ffh - ld t1rahi, #0ffh data bus 16-bit auto-reload register (t1ra) data latch t1 underflow interrupt instruction clock 16-bit auto-reload register (t1rb) 1 0 s t1rben reload select logic 16-bit timer (tmr1)
ace1502 product family arithmetic controller engine (acex ) for low power applications 16 www.fairchildsemi.com ace1502 product family rev. 1.7 5. write the appropriate control value to the t1cntrl register to select external event counter mode, to clock every falling edge, to set the enable bit, to clear the pending ag, and to start the counter. (see table 11 and table 12 ) - ld t1cntrl, #34h (#00h) ;setting the t1c0 bit starts the timer 6. when the counter under ows, the interrupt service routine must clear the t1pnd ag and take whatever action is required once the number of events occurs. if the software wishes to merely count the number of events and the antici- pated number may exceed 65,536, the interrupt service routine should record the number of under ows by incre- menting a counter in memory. software can then calculate the correct event count. - rbit t1pnd, t1cntrl ; t1pnd equals 3 figure 16. external event counter mode 4.4 mode 3: input capture mode in the input capture mode, the timer is used to measure elapsed time between edges of an input signal. once the timer is con gured for this mode, the timer starts counting down immediately at the instruction clock rate. the timer 1 will then transfer the current value of the tmr1 register into the t1ra register as soon as the selected edge of t1 is sensed. the input signal on t1 must have a pulse width equal to or greater than one instruction clock cycle. at every t1ra capture, software can then store the values into ram to calculate the elapsed time between edges on t1. at any given time (with proper con- sideration of the state of t1) the timer can be con gured to cap- ture on positive-going or negative-going edges. a block diagram of the timer s input capture mode of operation is shown in fig- ure 17. the timer has one interrupt (tmri1) that is maskable through the t1en bit of the t1cntrl register. however, the core is only interrupted if the t1en bit and the g (global interrupt enable) bit of the sr is set. the input capture mode contains two inter- rupt pending ags 1) the tmr1 register capture in t1ra (t1pnd) and 2) timer under ow (t1c0). if interrupts are enabled, the timer will generate an interrupt each time a pend- ing ag is set (provided that the pending ag was previously cleared.) the interrupt service routine is responsible for proper handling of the t1pnd ag, t1c0 ag, and the t1en bit. for this operating mode, the t1c0 control bit serves as the timer under ow interrupt pending ag. the timer 1 interrupt ser- vice routine must read both the t1pnd and t1c0 ags to deter- mine the cause of the interrupt. a set t1c0 ag means that a timer under ow occurred whereas a set t1pnd ag means that a capture occurred in t1ra. it is possible that both ags will be found set, meaning that both events occurred at the same time. the interrupt service routine should take this possibility into consideration. because the t1c0 bit is used as the under ow interrupt pend- ing ag, it is not available for use as a start/stop bit as in the other modes. the tmr1 register counts down continuously at the instruction clock rate starting from the time that the input capture mode is selected. (see table 11 and table 12) to stop the timer from running, you must change the mode to an alternate mode (pwm or external event counter) while resetting the t1c0 bit. the input pins can be independently con gured to sense posi- tive-going or negative-going transitions. the edge sensitivity of pin t1 is controlled by bit t1c1 as indicated in table 12. the edge sensitivity of a pin can be changed without leaving the input capture mode even while the timer is running. this feature allows you to measure the width of a pulse received on an input pin. for example, the t1 pin can be programmed to be sensitive to a positive-going edge. when the positive edge is sensed, the tmr1 register contents is transferred to the t1ra register and a timer 1 interrupt is generated. the timer 1 interrupt service routine records the contents of the t1ra register, changes the edge sensitivity from positive to negative-going edge, and clears the t1pnd ag. when the negative-going edge is sensed another timer 1 interrupt is generated. the interrupt service routine reads the t1ra register again. the difference between the previous reading and the current reading re ects the elapsed time between the positive edge and negative edge of the t1 input signal i.e. the width of the positive-going pulse. remember that the timer1 interrupt service routine must test the t1c0 and t1pnd ags to determine the cause of the inter- rupt. if the t1c0 ag caused the interrupt, the interrupt service routine should record the occurrence of an under ow by incre- menting a counter in memory or by some other means. the software that calculates the elapsed time between captures should take into account the number of under ow that occurred when making its calculation. the following steps show how to properly con gure timer 1 to operate in the input capture mode. 1. con gure t1 as an input by clearing bit 2 of portgc. - rbit 2, portgc ; con gure g2 as an input 2. initialize t1 to input with pull-up by setting bit 2 of portgd. - sbit 2, portgd ; set g2 high 3. enable the global interrupt enable bit. - sbit 4, status 4. with the timer stopped, load the initial time into the tmr1 register (typically the value is 0xffff.) - ld tmr1lo, #0ffh - ld tmr1hi, #0ffh 5. write the appropriate control value to the t1cntrl register to select input capture mode, to sense the appropriate edge, to set the enable bit, and to clear the pending ags. data bus 16-bit auto-reload register (t1ra) 16-bit counter (tmr1) t1 underflow interr upt edge selector logic
ace1502 product family arithmetic controller engine (acex ) for low power applications 17 www.fairchildsemi.com ace1502 product family rev. 1.7 (see table 11 and table 12) - ld t1cntrl, #64h ; t1c1 is the edge select bit 6. as soon as the input capture mode is enabled, the timer starts counting. when the selected edge is sensed on t1, the t1ra register is loaded and a timer 1 interrupt is triggered. figure 17. input capture mode 4.5 mode 4: difference input capture mode the difference input capture mode works similarly to the stan- dard input capture mode. however, for the difference input capture the timer automatically captures the elapsed time between the selected edges without the core needing to per- form the calculation. for example, the standard input capture mode requires that the timer be con gured to capture a particular edge (rising or fall- ing) at which time the timer s value is copied into the capture register. if the elapsed time is required, software must move the captured data into ram and recon gure the input capture mode to capture on the next edge (rising or falling). software must then subtract the difference between the two edges to yield useful information. the difference capture mode eliminates the need for software intervention and allows for capturing very short pulse or cycle widths. it can be con gured to capture the elapsed time between: 1. rising edge to falling edge 2. rising edge to rising edge 3. falling edge to rising edge 4. falling edge to falling edge once con gured, the difference capture timer waits for the rst selected edge. when the edge transition has occurred, the 16- bit timer starts counting up based every instruction clock cycle. it will continue to count until the second selected edge transition occurs at which time the timer stops and stores the elapse time into the t1ra register. software can now read the difference between transitions directly without using any processor resources. however, like the standard input capture mode both the capture (t1pnd) and the under ow (t1c0) ags must be monitored and handled appropriately. this feature allows the acex microcontroller to capture very small pulses where standard microcontrollers might have missed cycles due to the limited bandwidth. figure 18. difference capture mode 5. timer 0 timer 0 is a 12-bit free running idle timer. upon power-up or any reset, the timer is reset to 0x000 and then counts up continu- ously based on the instruction clock of 1mhz (1 s). software cannot read from or write to this timer. however, software can monitor the timer's pending (t0pnd) bit that is set every 8192 cycles (initially 4096 cycles after a reset). the t0pnd ag is set every other time the timer over ows (transitions from 0xfff to 0x000) through a divide-by-2 circuit. after an over ow, the timer will reset and restart its counting sequence. software can either poll the t0pnd bit or vector to an interrupt subroutine. in order to interrupt on a t0pnd, software must be sure to enable the timer 0 interrupt enable (t0inten) bit in the timer 0 control (t0cntrl) register and also make sure the g bit is set in sr. once the timer interrupt is serviced, software should reset the t0pnd bit before exiting the routine. timer 0 supports the following functions: 1. exiting from idle mode (see section 16 for details.) 2. start up delay from halt mode 3. watchdog pre-scalar (see section 6 for details.) the t0inten bit is a read/write bit. if set to 0, interrupt requests from the timer 0 are ignored. if set to 1, interrupt requests are accepted. upon reset, the t0inten bit is reset to 0. the t0pnd bit is a read/write bit. if set to 1, it indicates that a timer 0 interrupt is pending. this bit is set by a timer 0 over ow and is reset by software or system reset. the wkinten bit is used in the multi-input wakeup/interrupt block. see section 8 for details. figure 19. timer 0 control register de nition (t0cntrl) data bus 16-bit input capture register (t1ra) 16-bit timer (tmr1) t1 capture interr upt edge selector logic instruction cloc k underflow interr upt data bus 16-bit input capture register (t1ra) 16-bit timer (tmr1) t1 capture interr upt edge selector logic instruction cloc k underflow interrupt difference logic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wkinten x x x x x t0pnd t0inten
ace1502 product family arithmetic controller engine (acex ) for low power applications 18 www.fairchildsemi.com ace1502 product family rev. 1.7 6. watchdog the watchdog timer is used to reset the device and safely recover in the rare event of a processor runaway condition. the 12-bit timer 0 is used as a pre-scalar for watchdog timer. the watchdog timer must be serviced before every 61,440 cycles but no sooner than 4096 cycles since the last watchdog reset. the watchdog is serviced through software by writing the value 0x1b to the watchdog service (wdsvr) register (see figure 20). the part resets automatically if the watchdog is ser- viced too frequent, or not frequent enough. the watchdog timer must be enabled through the watchdog enable bit (wden) in the initialization register. the wden bit can only be set while the device is in programming mode. once set, the watchdog will always be powered-up enabled. software cannot disable the watchdog. the watchdog timer can only be disabled in programming mode by resetting the wden bit as long as the memory write protect (wdis) feature is not enabled. warning ensure that the watchdog timer has been serviced before entering idle mode because it remains operational during this time. figure 20. watchdog service register (wdsvr) 7. hardware bit-coder the hardware bit-coder is a dedicated hardware bit-encoding peripheral block, hardware bit-coder (hbc), for ir/rf data transmission (see figure 21.) the hbc is completely software programmable and can be con gured to emulate various bit- encoding formats. the software developer has the freedom to encode each bit of data into a desired pattern and output the encoded data at the desired frequency through either the g2 or g5 output (tx) ports. the hbc contains six 8-bit memory-mapped con guration reg- isters pscale, hpattern, lpattern, bpsel, hbcntrl, and dat0. the registers are used to select the transmission fre- quency, store the data bit-encoding patterns, con gure the data bit-pattern/frame lengths, and control the data transmission ow. to select the ir/rf transmission frequency, an 8-bit divide con- stant must be written into the ir/rf pre-scalar (pscale) regis- ter. the ir/rf transmission frequency generator divides the 1mhz instruction clock down by 4 and the pscale register is used to select the desired ir/rf frequency shift. together, the transmission frequency range can be con gured between 976hz (pscale = 0xff) and 125khz (pscale = 0x01). upon a reset, the pscale register is initialized to zero disabling the ir/rf transmission frequency generator. however, once the pscale register is programmed, the desired ir/rf frequency is maintained as long as the device is powered. once the transmission frequency is selected, the data bit- encoding patterns must be stored in the appropriate registers. the hbc contains two 8-bit bit-encoding pattern registers, high-pattern (hpattern) and low-pattern (lpattern). the encoding pattern stored in the hpattern register is transmit- ted when the data bit value to be encoded is a 1. similarly, the pattern stored in the lpattern register is transmitted when the data bit value to be encoded is a 0. the hbc transmits each encoded pattern msb rst. the number of bits transmitted from the hpattern and lpat- tern registers is software programmable through the bit period con guration (bpsel) register (see figure 22). during the transmission of hpattern, the number of bits transmitted is con gured by bph[2:0] (bpsel[2:0]) while bpl[2:0] (bpsel[5:3]) con gures the number of transmitted bits for the lpattern. the hbc allows from 2 (0x1) to 8 (0x7) encoding pattern bits to be transmitted from each register. upon a reset, bpsel is initially 0 disabling the hbc from transmitting pattern bits from either register. the data (dat0) register is used to store up to 8 bits of data to be encoded and transmitted by the hbc. this data is shifted, bit by bit, msb to lsb into a 1-bit decision register. if the active bit shifted into the decision register is 1, the pattern in the hpat- tern register is shifted out of the output port. similarly, if the active bit is 0 the pattern in the lpattern register is shifted out. the hbc control (hbcntrl) register is used to con gure and control the data transmission. hbcntrl is divided in 5 different controlling signal frame[2:0], iosel, txbusy, start / stop, and ocflag (see figure 23.) frame[2:0] selects the number of bits of dat0 to encode and transmit. the hbc allows from 2 (0x1) to 8 (0x7) dat0 bits to be encoded and transmitted. upon a reset, frame is initialized to zero disabling the dat0 s decision register transmitting no data. the iosel signal selects the transmission to output (tx) through either port g2 or g5. if iosel is 1, g5 is selected as the output port otherwise g2 is selected. the txbusy signal is read only and is used to inform software that a transmission is in progress. txbusy goes high when the encoded data begins to shift out of the output port and will remains high during each consecutive dat0 frame bit transmis- sion (see figure 25). the hbc will clear the txbusy signal when the last dat0 encoded bit of the frame is transmitted and the stop signal is 0. the start / stop signal controls the encoding and transmis- sion process for each data frame. when software sets the start / stop bit the dat0 frame transmission process begins. the start signal will remain high until the beginning of the last encoded dat0 frame bit transmission. the hbc then clears the start / stop bit allowing software to elect to either continue with a new dat0 frame transmission or stop the transmission all together (see figure 25). if txbusy is 0 when the start sig- nal is enabled, a synchronization period occurs before any data is transmitted lasting the amount of time to transmit a 0 encoded bit (see figure 24). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 1 1 0 1 1
ace1502 product family arithmetic controller engine (acex ) for low power applications 19 www.fairchildsemi.com ace1502 product family rev. 1.7 the ocflag signal is read only and goes high when the last encoded bit of the dat0 frame is transmitting. the ocflag sig- nal is used to inform software that the dat0 frame transmission operation is completing (see figure 25). if multiple dat0 frames are to be transmitted consecutively, software should poll the ocflag signal for a 1. once ocflag is 1, dat0 must be reload and the start / stop bit must be restored to 1 in order to begin the new frame transmission without interruptions (the synchronization period). since ocflag remains high during the entire last encoded dat0 frame bit transmission, software should wait for the hbc to clear the ocflag signal before poll- ing for the new ocflag high pulse. if new data is not reloaded into dat0 and the start signal (stop is active) is not set before the ocflag is 0, the transmission process will end (txbusy is cleared) and a new process will begin starting with the synchronization period. figure 24 and figure 25 shows how the hbc performs its data encoding. in the example, two frames are encoded and trans- mitted consecutively with the following bit encoding format spec- i cation: 1. transmission frequency = 62.5khz 2. data to be encoded = 0x52, 0x92 (all 8-bits) 3. each bit should be encoded as a 3-bit binary value, 1 = 110b and 0 = 100b 4. transmission output port : g2 to perform the data transmission, software must rst initialize the pscale, bpsel, hpattern, lpattern, and dat0 registers with the appropriate values. ld pscale, #03h ; (1mhz ?? 4) ?? 4 = 62.5khz ld bpsel, #012h ; bph = 2, bpl = 2 (3 bits each) ld hpattern, #0c0h ; hpattern = 0xc0 ld lpattern, #090h ; lpattern = 0x90 ld dat0, #052h ; dat0 = 0x52 once the basic registers are initialized, the hbc can be started. (at the same time, software must set the number of data bits per data frame and select the desired output port.) ld hbcntrl, #27h ; start / stop = 1, frame = 7, iosel = 0 after the hbc has started, software must then poll the ocflag for a high pulse and restore the dat0 register and the start signal to continue with the next data transmission. loop_hi: ifbit ocflag, hbcntrl ; wait for ocflag = 1 jp nxt_frame jp loop_hi nxt_frame: ld dat0, #092h ; dat0 = 0x92 sbit start, hbcntrl ; start / stop = 1 if software is to proceed with another data transmission, the ocflag must be zero before polling for the next ocflag high pulse. however, since the speci cation in the example requires no other data transmission software can proceed as desired. loop_lo: ifbit ocflag, hbcntrl ; wait for ocflag = 0 jp loop_lo etc. ; program proceeds as desired figure 21. hardware bit-coder (hbc) block diagram pscal e lpattern hpatter n down counte r dat 0 ir/rf cloc k 3 3 33 frame[2:0] [hbcntrl] bpl[2:0] [bpsel] bph[2:0] [bpsel] b7 shiftclk noshif t rfclk rfclk stopshift stopshift b7 b7 a b y ab y fixed clock divider by 4 8 g2 g 5 iosel hbcntrl[6 ] [pscale] cpu clock ocfla g ocflag hbcntrl[7] sync logi c start/stop hbcntrl[5] txbusy hbcntrl[4 ]
ace1502 product family arithmetic controller engine (acex ) for low power applications 20 www.fairchildsemi.com ace1502 product family rev. 1.7 figure 22. bit period con guration (bpsel) register figure 23. hbc control (hbcntrl) register figure 24. hbc signals for one byte message in pwm format figure 25. sending series of encoded messages bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 bpl[2:0] bph[2:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocflag iosel start / stop txbusy 0 frame[2:0] ocflag shiftclk bit 7 dat0 g2/g5 output ir/rf clock condition: bpsel = 0x12 [ "1", " 0 " = 3 * ir/rf clocks] dat0 = 0x52 no. bit to encode = 8 (hbcntrl = xxxx0111b) "0" "1" "1" "0" "1" "0" "0" "0" start/stop txb usy "0" start/stop ocflag shiftclk bit 7 dat0 g2/g5 output ir/rf clock conditions: bpsel = 0x12 [ "1", " 0 " = 3 * ir/rf clocks] dat0 = 0x52 , 0x92 no. bit to encode = 8 (hbcntrl = xxxx0111b) txb usy "0" "1" "1" "0" "1" "0" "0" "0" "1" "0" "1" "0" "0" "0" "0" "1" software must set the start bit while ocflag is set in order to send another message without introducing a delay . stop bit clear, transmission ends . "0"
ace1502 product family arithmetic controller engine (acex ) for low power applications 21 www.fairchildsemi.com ace1502 product family rev. 1.7 8. multi-input wakeup/interrupt block the multi-input wakeup (miw)/interrupt contains three memory-mapped registers associated with this circuit: wkedg (wakeup edge), wken (wakeup enable), and wkpnd (wakeup pending). each register has 8-bits with each bit corresponding to an input pins as shown in figure 27. all three registers are initialized to zero upon reset. the wkedg register establishes the edge sensitivity for each of the wake-up input pin: either positive going-edge (0) or negative-going edge (1). the wken register enables (1) or disables (0) each of the port pins for the wakeup/interrupt function. the wakeup i/os used for the wakeup/interrupt function must also be con gured as an input pin in its associated port con guration register. however, an interrupt of the core will not occur unless interrupts are enabled for the block via bit 7 of the t0cntrl register (see fig- ure 19) and the g (global interrupt enable) bit of the sr is set. the wkpnd register contains the pending ags corresponding to each of the port pins (1 for wakeup/interrupt pending, 0 for wakeup/interrupt not pending). if an i/o is not selected to become a wakeup input, the pending ag will not be generated. to use the multi-input wakeup/interrupt circuit, perform the steps listed below making sure the miw edge is selected before enabling the i/o to be used as a wakeup input thus preventing false pending ag generation. this same procedure should be used following any type of reset because the wakeup inputs are left oating after resets resulting in unknown data on the port inputs. 1. clear the wken register. - clr wken 2. clear the wkpnd register to cancel any pending bits. - clr wkpnd 3. if necessary, write to the port con guration register to select the desired port pins to be con gured as inputs. - rbit 4, portgc ; g4 4. if necessary, write to the port data register to select the desired port pins input state. - sbit 4, portgd ; pull-up 5. write the wkedg register to select the desired type of edge sensitivity for each of the pins used. - ld wkedg, #0ffh ; all negative-going edges 6. set the wken bits associated with the pins to be used, thus enabling those pins for the wakeup/interrupt function. - ld wken, #10h ; enabling g4 once the multi-input wakeup/interrupt function has been con- gured, a transition sensed on any of the i/o pins will set the corresponding bit in the wkpnd register. the wkpnd bits, where the corresponding enable (wken) bits are set, will bring the device out of the halt mode and can also trigger an inter- rupt if interrupts are enabled. the interrupt service routine can read the wkpnd register to determine which pin sensed the interrupt. the interrupt service routine or other software should clear the pending bit. the device will not enter halt mode as long as a wkpnd pending bit is pending and enabled. the user has the responsibility of clearing the pending ags before attempting to enter the halt mode. upon reset, the wkedg register is con gured to select posi- tive-going edge sensitivity for all wakeup inputs. if the user wishes to change the edge sensitivity of a port pin, use the fol- lowing procedure to avoid false triggering of a wakeup/interrupt condition. 1. clear the wken bit associated with the pin to disable that pin. 2. clear the wkpnd bit associated with the pin. 3. write the wkedg register to select the new type of edge sensitivity for the pin. 4. set the wken bit associated with the pin to re-enable it. portg provides the user with three fully selectable, edge sen- sitive interrupts that are all vectored into the same service sub- routine. the interrupt from portg shares logic with the wakeup circuitry. the wken register allows interrupts from portg to be individually enabled or disabled. the wkedg register speci- es the trigger condition to be either a positive or a negative edge. the wkpnd register latches in the pending trigger condi- tions. since portg is also used for exiting the device from the halt mode, the user can elect to exit the halt mode either with or without the interrupt enabled. if the user elects to disable the interrupt, then the device restarts execution from the point at which it was stopped ( rst instruction cycle of the instruction fol- lowing halt mode entrance instruction). in the other case, the device nishes the instruction that was being executed when the part was stopped and then branches to the interrupt service routine. the device then reverts to normal operation. figure 26. multi-input wakeup (miw) register bit assignments 9. available only on the 14-pin package option wkedg, wken, wkpnd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 9 g7 9 g6 g5 g4 g3 g2 g1 g0
ace1502 product family arithmetic controller engine (acex ) for low power applications 22 www.fairchildsemi.com ace1502 product family rev. 1.7 figure 27. multi-input wakeup (miw) block diagram 10. wkinten: bit 7 of t0cntrl 9. i/o port the eight i/o pins (six on 8-pin package option) are bi- directional (see figure 28). the bi-directional i/o pins can be individually con gured by software to operate as high- impedance inputs, as inputs with weak pull-up, or as push-pull outputs. the operating state is determined by the contents of the corresponding bits in the data and con guration registers. each bi-directional i/o pin can be used for general purpose i/o, or in some cases, for a speci c alternate function determined by the on-chip hardware. figure 28. portgd logic diagram 9.1 i/o registers the i/o pins (g0-g7) have three memory-mapped port regis- ters associated with the i/o circuitry: a port con guration regis- ter (portgc), a port data register (portgd), and a port input register (portgp). portgc is used to con gure the pins as inputs or outputs. a pin may be con gured as an input by writing a 0 or as an output by writing a 1 to its corresponding portgc bit. if a pin is con gured as an output, its portgd bit repre- sents the state of the pin (1 = logic high, 0 = logic low). if the pin is con gured as an input, its portgd bit selects whether the pin is a weak pull-up or a high-impedance input. table 13 pro- vides details of the port con guration options. the port con gu- ration and data registers can both be read from or written to. reading portgp returns the value of the port pins regardless of how the pins are con gured. since this device supports miw, portg inputs have schmitt triggers. figure 29. i/o register bit assignments 11. available only on the 14-pin package option 12. g3 after reset is an input with weak pull-up table 13. i/o con guration options edgei wkout data bus 7 0 wken[7:0] 0 7 wkedg[0:7] wkpnd[0:7] g7 g0 wkinten 10 gxpullen gxbufen gxout gxin g x portgc, portgd, portgd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11 g7 11 g6 g5 g4 12 g3 g2 g1 g0 con guration bit data bit port pin con guration 0 0 high-impedence input (tri-state input) 0 1 input with pull-up (weak one input) 1 0 push-pull zero output 1 1 push-pull one output
ace1502 product family arithmetic controller engine (acex ) for low power applications 23 www.fairchildsemi.com ace1502 product family rev. 1.7 10. in-circuit programming speci cation the acex microcontroller supports in-circuit programming of the internal data eeprom, code eeprom, and the initializa- tion registers. in order to enter into program mode a 10-bit opcode (0x34b) must be shifted into the ace1502 while the device is executing the internal power on reset (t reset ). the shifting protocol fol- lows the same timing rules as the programming protocol de ned in figure 30. the opcode is shifted into the ace1502 serially, msb rst, with the data being valid by the rising edge of the clock. once the pattern is shifted into the device, the current 10-bit pattern is matched to protocol entrance opcode of 0x34b. if the 10-bit pattern is a match, the device will enable the internal program mode ag so that the device will enter into program mode once reset has completed (see figure 30.) the opcode must be shifted in after vcc settles to the nominal level and should end before the power on reset sequence (t reset ) completes; otherwise, the device will start normal execution of the program code. if the external reset is applied by bringing the reset pin low, once the reset pin is release the opcode may now be shifted in and again should end before the reset sequence completes. 10.3 programming protocol after placing the device in program, the programming protocol and commands may be issued. an externally controlled four-wire interface consisting of a load control pin (g3), a serial data shift-in input pin (g4), a serial data shift-out output pin (g2), and a clock pin (g1) is used to access the on-chip memory locations. communication between the acex microcontroller and the external programmer is made through a 32-bit command and response word described in table 14. be sure to either oat or tie g5 to vcc for proper programming functionality. the serial data timing for the four-wire interface is shown in fig- ure 31 and the programming protocol is shown in figure 30. 10.3.1 write sequence the external programmer brings the acex microcontroller into programming then needs to set the load pin to vcc before shifting in the 32-bit serial command word using the shift_in and clock signals. by de nition, bit 31 of the command word is shifted in rst. at the same time, the acex microcontroller shifts out the 32-bit serial response to the last command on the shift_out pin. it is recommended that the external program- mer samples this signal t access (500 ns) after the rising edge of the clock signal. the serial response word, sent immedi- ately after entering programming mode, contains indeterminate data. after 32 bits have been shifted into the device, the external pro- grammer must set the load signal to 0v, and then apply two clock pulses as shown in figure 30 to complete program cycle. the shift_out pin acts as the handshaking signal between the device and programming hardware once the load signal is brought low. the device sets shift_out low by the time the programmer has sent the second rising edge during the load = 0v phase (if the timing speci cations in figure 30 are obeyed). the device will set the r bit of the status register when the write operation has completed. the external programmer must wait for the shift_out pin to go high before bringing the load sig- nal to vcc to initiate a normal command cycle. 10.3.2 read sequence when reading the device after a write, the external programmer must set the load signal to vcc before it sends the new com- mand word. next, the 32-bit serial command word (for during a read) should be shifted into the device using the shift_in and the clock signals while the data from the previous com- mand is serially shifted out on the shift_out pin. after the read command has been shifted into the device, the external programmer must, once again, set the load signal to 0v and apply two clock pulses as shown in figure 30 to complete read cycle. data from the selected memory location, will be latched into the lower 8 bits of the command word shortly after the second rising edge of the clock signal. writing a series of bytes to the device is achieved by sending a series of write command words while observing the devices handshaking requirements. reading a series of bytes from the device is achieved by send- ing a series of read command words with the desired addresses in sequence and reading the following response words to verify the correct address and data contents. the addresses of the data eeprom and code eeprom locations are the same as those used in normal operation. powering down the device will cause the part to exit program- ming mode. table 14 32-bit command and response word bit number input command word output response word bits 31-30 must be set to 0 x bit 29 set to 1 to read/write data eeprom, or the initialization registers, otherwise 0 x bit 28 set to 1 to read/write code eeprom, otherwise 0 x bits 27-25 must be set to 0 x bit 24 set to 1 to read, 0 to write x bits 23-19 must be set to 0 x bits 18 -8 address of the byte to be read or written same as input command word bits 7-0 data to be programmed or zero if data is to be read programmed data or data read at speci ed address
ace1502 product family arithmetic controller engine (acex ) for low power applications 24 www.fairchildsemi.com ace1502 product family rev. 1.7 figure 30. programming protocol 13 13. during in-circuit programming, g5 must be either not connected or driven high. figure 31. serial data timing 11. brown-out/low battery detect circuit the brown-out reset (bor) and low battery detect (lbd) circuits on the acex microcontroller have been designed to offer two types of voltage reference comparators. the sections below will describe the functionality of both circuits. figure 32. bor/lbd block diagram vcc load (g3) clock (g1) shift_in (g4) shift_out (g2) (in write mode) bit 31 bit 30 bit 0 bit 31 shift_out (g2) (in read mode) a: start of programming cycle 32 clock pulses t load2 busy ready a t load4 t load3 t ready busy low by 2nd clock pulse t load1 11 1 1 11 000 0 10-bit opcode = 0x34b t reset a reset v alid v alid shift_out (g2) shift_in (g4) clock (g1) t hi t lo t dis t dih t doh t dos t a ccess 7 bl[4] 6 bl[3] 5 bl[2] 4 bl[1] 3 bl[0] 2 vsel 1 x 0 lbd adjust reference voltage lbd control register to reset logic vcc 1 0 s g4 +1.8v vref + _ lbd + _ bor
ace1502 product family arithmetic controller engine (acex ) for low power applications 25 www.fairchildsemi.com ace1502 product family rev. 1.7 11.1 brown-out reset the brown-out reset (bor) function is used to hold the device in reset when vcc drops below a xed threshold (1.83v.) while in reset, the device is held in its initial condition until vcc rises above the threshold value. shortly after vcc rises above the threshold value, an internal reset sequence is started. after the reset sequence, the core fetches the rst instruction and starts normal operation. the bor should be used in situations when vcc rises and falls slowly and in situations when vcc does not fall to zero before rising back to operating range. the brown-out reset can be thought of as a supplement function to the power-on reset if vcc does not fall below ~1.5v. the power-on reset circuit works best when vcc starts from zero and rises sharply. in applica- tions where vcc is not constant, the bor will give added device stability. the bor circuit must be enabled through the bor enable bit (boren) in the initialization register. the boren bit can only be set while the device is in programming mode. once set, the bor will always be powered-up enabled. software cannot dis- able the bor. the bor can only be disabled in programming mode by resetting the boren bit as long as the global write protect (wdis) feature is not enabled. figure 33. bor and por circuit relationship diagram 11.2 low battery detect the low battery detect (lbd) circuit allows software to monitor the vcc level at the lower voltage ranges. lbd has a 32-level software programmable voltage reference threshold that can be changed on the y. once vcc falls below the selected threshold, the lbd ag in the lbd control register is set. the lbd ag will hold its value until vcc rises above the threshold. (see table 15) the lbd bit is read only. if lbd is 0, it indicates that the vcc level is higher than the selected threshold. if lbd is 1, it indi- cates that the vcc level is below the selected threshold. the threshold level can be adjusted up to eight levels using the three trim bits (bl[4:0]) of the lbd control register. the lbd ag does not cause any hardware actions or an interruption of the proces- sor. it is for software monitoring only. the vsel bit of the lbd control register can be used to select an external voltage source rather than vcc. if vsel is 1, the voltage source for the lbd comparator will be an input voltage provided through g4. if vsel is 0, the voltage source will be vcc. the lbd circuit must be enabled through the lbd enable bit (lbden) in the initialization register. the lbden bit can only be set while the device is in programming mode. once set, the lbd will always be powered-up enabled. software cannot disable the lbd. the lbd can only be disabled in programming mode by resetting the lbden bit as long as the global write protect (wdis) feature is not enabled. the lbd circuit is disabled during halt/idle mode. after exit- ing halt/idle, software must wait at lease 10 s before read- ing the lbd bit to ensure that the internal circuit has stabilized. vcc (pin 8) reset circuit output global reset to logic external reset pin (14-pin only) b a por (pin 7 ) vcc time bor output 1.75 0 vcc vcc 0 por output por output pulse 1.8v 0 vcc 5.0v 0 the reset circuit will trigger when inputs a or b transition from high to low. at that time the global reset signal will go high which will res et all controller logic. the global reset will go high and stay high for around 1us. vcc bor output output
ace1502 product family arithmetic controller engine (acex ) for low power applications 26 www.fairchildsemi.com ace1502 product family rev. 1.7 table 15. lbd control register de nition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bl[4:0] vsel x lbd level bl[4] bl[3] bl[2] bl[1] bl[0] voltage reference range (typical) 1 0 0 0 0 0 1.81v 2 0 0 0 0 1 1.87v 3 0 0 0 1 0 1.93v 4 0 0 0 1 1 1.99v 5 0 0 1 0 0 2.05v 6 0 0 1 0 1 2.11v 7 0 0 1 1 0 2.17v 8 0 0 1 1 1 2.23v 9 0 1 0 0 0 2.29v 10 0 1 0 0 1 2.36v 11 0 1 0 1 0 2.42v 12 0 1 0 1 1 2.48v 13 0 1 1 0 0 2.54v 14 0 1 1 0 1 2.60v 15 0 1 1 1 0 2.66v 16 0 1 1 1 1 2.72v 17 1 0 0 0 0 2.77v 18 1 0 0 0 1 2.84v 19 1 0 0 1 0 2.91v 20 1 0 0 1 1 2.97v 21 1 0 1 0 0 3.03v 22 1 0 1 0 1 3.09v 23 1 0 1 1 0 3.16v 24 1 0 1 1 1 3.22v 25 1 1 0 0 0 3.28v 26 1 1 0 0 1 3.34v 27 1 1 0 1 0 3.41v 28 1 1 0 1 1 3.47v 29 1 1 1 0 0 3.54v 30 1 1 1 0 1 3.60v 31 1 1 1 1 0 3.67v 32 1 1 1 1 1 3.73v
ace1502 product family arithmetic controller engine (acex ) for low power applications 27 www.fairchildsemi.com ace1502 product family rev. 1.7 12. reset block when a reset sequence is initiated, all i/o registers will be reset setting all i/os to high-impedence inputs. the system clock is restarted after the required clock start-up delay. a reset is generated by any one of the following four conditions: power-on reset (as described in section 13) brown-out reset (as described in section 11.1) watchdog reset (as described in section 6) external reset 18 (as described in section 13) 18. available only on the 14-pin package option 13. power-on reset the power-on reset (por) circuit is guaranteed to work if the rate of rise of vcc is no slower than 10ms/1volt. the por circuit was designed to respond to fast low to high transitions between 0v and vcc. the circuit will not work if vcc does not drop to 0v before the next power-up sequence. in applications where 1) the vcc rise is slower than 10ms/1 volt or 2) vcc does not drop to 0v before the next power-up sequence the external reset option should be used. the external reset provides a way to properly reset the acex microcontroller if por cannot be used in the application. the external reset pin contains an internal pull-up resistor. there- fore, to reset the device the reset pin should be held low for at least 2ms so that the internal clock has enough time to stabilize. 14. clock the acex microcontroller has an on-board oscillator trimmed to a frequency of 2mhz who is divided down by two yielding a 1mhz frequency. (see ac electrical characteristics) upon power-up, the on-chip oscillator runs continuously unless enter- ing halt mode or using an external clock source. if required, an external oscillator circuit may be used depending on the states of the cmode bits of the initialization register. (see table 16) when the device is driven using an external clock, the clock input to the device (g1/cki) can range between dc to 4mhz. for external crystal con guration, the output clock (cko) is on the g0 pin. (see figure 34.) if the device is con g- ured for an external square clock, it will not be divided. table 16. cmodex bit de nition figure 34. crystal 15. halt mode the halt mode is a power saving feature that almost com- pletely shuts down the device for current conservation. the device is placed into halt mode by setting the halt enable bit (ehalt) of the halt register through software using only the ld m, # instruction. ehalt is a write only bit and is automati- cally cleared upon exiting halt. when entering halt, the inter- nal oscillator and all the on-chip systems including the lbd and the bor circuits are shut down. the device can exit halt mode only by the miw circuit. there- fore, prior to entering halt mode, software must con gure the miw circuit accordingly. (see section 8) after a wakeup from halt, a 1ms start-up delay is initiated to allow the internal oscil- lator to stabilize before normal execution resumes. immediately after exiting halt, software must clear the power mode clear (pmc) register by only using the ld m, # instruction. (see fig- ure 36) figure 35. halt register de nition cmode [1] cmode [0] clock type 0 0 internal 1 mhz clock 0 1 external square clock 1 0 external crystal/resonator 1 1 reserved r 2 c 2 cki ck o r 1 c 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unde ned unde ned unde ned unde ned unde ned unde ned eidle ehalt
ace1502 product family arithmetic controller engine (acex ) for low power applications 28 www.fairchildsemi.com ace1502 product family rev. 1.7 figure 36. recommended halt flow 16. idle mode in addition to the halt mode power saving feature, the device also supports an idle mode operation. the device is placed into idle mode by setting the idle enable bit (eidle) of the halt register through software using only the ld m, # instruc- tion. eidle is a write only bit and is automatically cleared upon exiting idle. the idle mode operation is similar to halt except the internal oscillator, the watchdog, and the timer 0 remain active while the other on-chip systems including the lbd and the bor circuits are shut down. the device automatically wakes from idle mode by the timer 0 over ow every 8192 cycles (see section 5). before entering idle mode, software must clear the wken register to disable the miw block. once a wake from idle mode is triggered, the core will begin normal operation by the next clock cycle. imme- diately after exiting idle mode, software must clear the power mode clear (pmc) register by using only the ld m, # instruc- tion. (see figure 37.) figure 37. recommended idle flow normal mode halt mode resume normal mod e ld halt, #01 h ld pmc, #00 h multi-input wakeup normal mode idle mode resume normal mode ld pmc, #00h timer0 underflow multi-input wakeup ld halt, #02h
ace1502 product family arithmetic controller engine (acex ) for low power applications 29 www.fairchildsemi.com ace1502 product family rev. 1.7 ordering information part number core type max. # i/os program memory size operating voltage range package tape & reel 0125 8 1k 2k 1.8 3.6v -40 to +85 c -40 to +125 c 8-pin soic 14-pin soic 8-pin dip 14-pin dip 8-pin tssop 14-pin tssop ace1502em8 x x x x x x ace1502em8x x x x x x x x ace1502em x x x x x x ace1502emx x x x x x x x ace1502emt8 x x x x x x ace1502emt8x x x x x x x x ace1502emt x x x x x x ACE1502EMTX x x x x x x x ace1502en x x x x x x ace1502en14 x x x x x x ace1502vm8 x x x x x x ace1502vm8x x x x x x x x ace1502vm x x x x x x ace1502vmx x x x x x x x ace1502vmt8 x x x x x x ace1502vmt8x x x x x x x x ace1502vmt x x x x x x ace1502vmtx x x x x x x x ace1502vn x x x x x x ace1502vn14 x x x x x x
ace1502 product family arithmetic controller engine (acex ) for low power applications 30 www.fairchildsemi.com ace1502 product family rev. 1.7 physical dimensions inches (millimeters) unless otherwise noted) 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.004 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 molded small out-line package (m8) order number ace1502em8/ace1502vm8 package number m08a 8-pin dip (n) order number ace1502en/ace1502vn package number n08a
ace1502 product family arithmetic controller engine (acex ) for low power applications 31 www.fairchildsemi.com ace1502 product family rev. 1.7 physical dimensions inches (millimeters) unless otherwise noted) 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0118 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0-8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x 5.0 0.1 3.2 6.4 17 14 8 4.4 0.1 (7.72) typ (4.16) typ (1.78) typ (0.42) typ 0.2 c b a (0.65) typ 0.10 0.05 typ all lead tips 0.65 typ. 1.1 max typ 0.19 - 0.30 typ pin #1 ident 0.9 - 0.20 typ (0.9) 0 -8 0.6 0.1 0.25 seating plane gage plane see detail a dimensions are in millimeters notes: unless otherwise specified 1. reference jeded registration mo153. variation ab. ref. note 6, dated 7/93 land pattern recommendation detail a typ. scale: 40x - a - - b - - c - 0.13 c s b a s m 0.1 c all lead tips 8-pin tssop order number ace1502emt8/ace1502vmt8 package number mt08a 14-pin tssop order number ace1502emt/ace1502vmt package number mt14a
ace1502 product family arithmetic controller engine (acex ) for low power applications 32 www.fairchildsemi.com ace1502 product family rev. 1.7 physical dimensions inches (millimeters) unless otherwise noted) 123 4567 14 13 12 11 10 9 8 0.335 - 0.344 (8.509 - 8.788) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. molded small out-line package (m) order number ace1502em/ace1502em package number m14a 14-pin dip (n14) order number ace1502en14/ace1502vn14 package number n14a
33 www.fairchildsemi.com ace1502 product family rev. 1.7 ace1502 product family arithmetic controller engine (acex ) for low power applications life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 acex development tools general information: fairchild semiconductor offers different possibilities to evaluate and emulate software written for acex. simulator : is a windows program able to load, assemble, and debug acex programs. it is possible to place as many break- points as needed, trace the program execution in symbolic for- mat, and program a device with the proper options. the acex simulator is available free-of-charge and can be downloaded from fairchild s web site at www.fairchildsemi.com/products/ memory/ace acex emulator kit : fairchild also offers a low cost real-time in- circuit emulator kit that includes: emulator board emulator software assembler and manuals power supply dip14 target cable pc cable the acex emulator allows for debugging the program code in a symbolic format. it is possible to place one breakpoint and watch various data locations. it also has built-in programming capability. prototype board kits : fairchild offers two solutions for the sim- pli cation of the breadboard operation so that acex applica- tions can be quickly tested. 1) acedemo can be used for general purpose applications 2) acetxrx is for transmitting / receiving (rf, ir, rs232, rs485) applications. acedemo has 8 switches, 8 leds, rs232 voltage translator, buzzer, and a lamp with a small breadboard area. factory programming: fairchild offers factory pre-programming and serialization (for justi ed quantities) for a small additional cost. please refer to your local distributor for details regarding factory programming. ordering p/ns emulator kit and programming adapters: please refer to your local distributor for details regarding devel- opment tools.

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